Mobile radio frequency (RF) chip designs (e.g., mobile RF transceivers) have migrated to deep sub-micron process nodes due to cost and power consumption considerations. The design complexity of mobile RF transceivers is further complicated by added circuit function to support communication enhancements. Further design challenges for mobile RF transceivers include analog/RF performance considerations, including mismatch, noise, and other performance considerations. The design of these mobile RF chips include the use of a phase locked loop (PLL), for example, to generate an output signal with a phase related to a phase of an input signal.
The PLL is a closed-loop frequency-control system based on a phase difference between the input clock signal and a feedback clock signal of a controlled oscillator. The main blocks of the PLL are the phase frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and counters, such as a feedback counter (M), a pre-scale counter (N), and post-scale counters (C).
In phase locked loop (PLL) structures, particularly in frequency synthesizers (FS), a phase frequency detector (PFD) is often used instead of the conventional phase detector (PD). Compared with the PD, the PFD has both phase and the frequency sensitivity and an input range up to +/−2π, which enables increasing of the acquisition range and locking speed of the tracking system.
In practice, some issues arise with implementation of the PFD, such as non-linearity of the dynamic transfer characteristic (TC) and direct current (DC) offset of the output signal. Mainly, the non-linearity is caused by the finite speed (time delays) of the components used (dynamic errors) as well as by tolerances and mismatching of the component parameters (static errors).